Capacitance characterization of tapered through-silicon-via considering MOS effect

In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal–oxide–semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 751, 801, 851 and 901. It is shown that error is less than 5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 801 for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5 μm), dielectric liner thickness (from 0.1 to 0.5 μm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50 μm) and acceptor concentration (from 1 10 to 5 10 cm ) cause increase of T-TSV capacitance by about 25 fF, 12 fF, 12 fF, 210 fF and 12 fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained. & 2013 Elsevier Ltd. All rights reserved.